Crosstalk in Modern On-Chip Interconnects: A FDTD Approach by B.K. Kaushik, V. Ramesh Kumar, Amalendu Patnaik

By B.K. Kaushik, V. Ramesh Kumar, Amalendu Patnaik

The publication presents exact FDTD types for on-chip interconnects, masking latest developments in fabrics and layout. moreover, counting on the geometry and actual configurations, diversified electric identical types for CNT and GNR established interconnects are awarded. in accordance with an identical versions the functionality comparability one of the Cu, CNT and GNR-based interconnects also are mentioned within the booklet. The proposed types are established with the HSPICE simulations.

The publication introduces the present study state of affairs within the modeling of on-chip interconnects. It provides the constitution, homes, and features of graphene established on-chip interconnects and the FDTD modeling of Cu established on-chip interconnects. The version considers the non-linear results of CMOS motive force in addition to the transmission line results of interconnect line that comes with coupling capacitance and mutual inductance results. In a extra life like demeanour, the proposed version contains the impact of width-dependent MFP of the MLGNR whereas considering the sting roughness.

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Extra resources for Crosstalk in Modern On-Chip Interconnects: A FDTD Approach

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In: Proceedings of the IEEE international interconnect technology conference, pp 234–36 32. Forró L, Schönenberger C (2000) Physical properties of multi-wall nanotubes in topics in applied physics, carbon nanotubes: synthesis, structure, properties and applications. In: Dresselhaus MS, Dresselhaus G, Avouris P (eds) Springer-Verlag, Berlin, Germany 33. Wei BQ, Vajtai R, Ajayan PM (2001) Reliability and current carrying capacity of carbon nanotubes. Appl Phys Lett 79(8):1172–1174 34. Close GF, Wong HSP (2008) Assembly and electrical characterization of multiwall carbon nanotube interconnects.

17. The permittivity of the medium between the bottommost layer of MLGNR and the ground plane is represented by ε. The total number of layers (Nlayer) can be expressed as Nlayer ¼ 1 þ int hti ð2:22Þ d Fig. 3 Graphene Nanoribbons N RMC 2 N 35 rsN RQN lkN RQN leN N RMC 2 N N cq Topmost layer 2 RMC N −1, N lm RQ2 2 2 lk rs 2 N −1, N cm RQ2 2 le 1,N lm 1,2 2 RMC 2 cq2 lm c1,2 m 1 RMC 1 RQ1 rs 1 1 RQ1 1 lk le 1 RMC 1 1 cq Bottommost layer ce Fig. 34 nm for doped and neutral MLGNRs [77], respectively.

38 2 Interconnect Modeling, CNT and GNR Structures, Properties, and Characteristics References 1. Livshits P, Sofer S (2012) Aggravated electromigration of copper interconnection lines in ULSI devices due to crosstalk noise. IEEE Trans Device Mater Reliab 12(2):341–346 2. Moll F, Roca M, Rubio A (1998) Inductance in VLSI interconnection modeling. IEEE Proc Circuits Devices Syst 145(3):175–179 3. Sakurai T, Newton R (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas.

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